Solid state drive (SSD) devices commonly employ NAND flash memory chips and a flash controller to manage the flash memory and to transfer data between the flash memory and a host computer. Uncorrectable Bit Error Rates (UBER) requirements for client and enterprise Solid State Drives (SSD's) are very stringent, requiring UBER of 10−15 for client SSD's and 10−16 for enterprise SSD's. Error correction codes have been widely adopted to obtain the low Bit Error Rate (BER) required to achieve these low UBER requirements. Driven by cost, the NAND industry keeps pushing hard on process technology shrink. Technology shrink has been successful in increasing the number of Gbit per mm2, but this success has resulted in increased BER of NAND flash memory chips and SSD's that use NAND flash memory chips.
Standard read operations are performed over the lifetime of the SSD. However, as the NAND devices in the SSD age and are subjected to numerous read, program and erase (P/E) cycles, the BER increases, ultimately resulting in decode failures in which the decoding process is unsuccessful in recovering the stored codeword. Conventional flash management techniques have extended the lifetime of SSD's by performing a read retry immediately after a failed standard read operation, allowing the SSD to recover the codeword that was not recovered in the original read operation. However, the price that is paid for this extension of the SSD's life is increased read latency. When read retry is triggered as a result of a decode failure, the latency of the SSD is increased by the time required to perform the standard read operation plus the time required for the read retry operation. This presents a problem. Accordingly, there is a need for a method and apparatus that will reduce read latency and that will meet stringent UBER requirements.